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1 Z86C21 mcu with 8k rom p roduct s pecifica tion n 8-bit cmos mcu with 8 kbytes of rom n 256 byte register file - 236 bytes of general-purpose ram - 16 bytes control/status registers - 4 bytes for ports n 40-pin dip, 44-pin plcc or 44-pin qfp package n 4.5v to 5.5v operating range n low power consumption: 220 mw (max) @ 16 mhz n fast instruction pointer: 1.0 m s @ 12 mhz n two standby modes: stop and halt n 32 input/output lines features Z86C21 8k rom z8 ? cmos m icrocontroller n full-duplex uart n all digital inputs are ttl levels n auto latches n ram and rom protect n two programmable 8-bit counter/timers each with 6-bit programmable prescaler. n six vectored, priority interrupts from eight different sources n clock speeds: 12 and 16 mhz n on-chip oscillator that accepts a crystal, ceramic resonator, lc, or external clock drive. general description the Z86C21 microcontroller is a member of the z8 single- chip microcontroller family with 8 kbytes of rom and 236 bytes of ram. the device is packaged in a 40-pin dip, 44-pin plcc, or a 44-pin qfp with a romless pin option available on the 44-pin versions only. with the rom/ romless feature selectively, the Z86C21 offers both exter- nal memory and preprogrammed rom, making it well- suited for high-volume applications or where code flexibil- ity is required. zilogs cmos microcontroller offers fast execution, effi- cient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. the Z86C21 architecture is characterized by zilogs 8-bit microcontroller core. the device offers a flexible i/o scheme, an efficient register and address space structure, multiplexed capabilities between address/data, i/o, and a number of ancillary features that are useful in many indus- trial and advanced scientific applications. for applications demanding powerful i/o capabilities, the Z86C21 provides 32 pins dedicated to input and output. these lines are grouped into four ports. each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel i/o with or without handshake, and an address/data bus for interfacing external memory. there are three basic address spaces available to support this configuration: program memory, data memory, and 236 general-pur- pose registers.
\2 Z86C21 mcu with 8k rom general description (continued) to unburden the program from coping with the real-time tasks, such as counting/timing and serial data communi- cation, the Z86C21 offers two on-chip counter/timers with a large number of user selectable modes, and an on-board uart. port 3 uart counter/ timers (2) interrupt control port 2 i/o (bit programmable) alu flags register pointer register file 256 x 8-bit machine timing and instruction control prg. memory 8192 x 8-bit program counter vcc gnd xtal 44 port 0 output input address or i/o (nibble programmable) 8 port 1 address/data or i/o (byte programmable) /as /ds r//w /reset figure 1. Z86C21 functional block diagram notes: all signals with a preceding front slash, "/", are active low, e.g., b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss
3 Z86C21 mcu with 8k rom pin description pin # symbol function direction 1v cc power supply input 2 xtal2 crystal, oscillator clock output 3 xtal1 crystal, oscillator clock input 4 p37 port 3, pin 7 output 5 p30 port 3, pin 0 input 6 /reset reset input 7 r//w read/write output 8 /ds data strobe output 9 /as address strobe output 10 p35 port 3, pin 5 output pin # symbol function direction 11 gnd ground input 12 p32 port 3, pin 2 input 13-20 p00-p07 port 0, pins 0,1,2,3,4,5,6,7 in/output 21-28 p10-p17 port 1, pins 0,1,2,3,4,5,6,7 in/output 29 p34 port 3, pin 4 output 30 p33 port 3, pin 3 input 31-38 p20-p27 port 2, pins 0,1,2,3,4,5,6,7 in/output 39 p31 port 3, pin 1 input 40 p36 port 3, pin 6 output table 1. 40-pin dip pin identification 1 2 9 3 4 5 6 7 8 40 39 38 37 36 35 34 33 32 p36 p31 p21 p27 p26 p25 p24 p23 p22 vcc xtal2 p37 p30 /reset r//w /ds 31 30 29 28 27 14 10 11 12 13 xtal1 gnd p32 p00 p01 p20 p33 p34 p17 p16 Z86C21 dip 15 26 25 24 23 22 21 20 16 17 18 19 /as p35 p02 p03 p06 p07 p05 p04 p13 p15 p14 p12 p11 p10 figure 2. 40-pin dip pin assignments
\4 Z86C21 mcu with 8k rom pin description (continued) n/c p30 p37 xtal1 xtal2 vcc p36 p31 p27 p26 p25 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 n/c n/c p24 p23 p22 p21 p20 p33 p34 p17 p16 p15 /reset r//w /ds /as p35 gnd p32 p00 p01 p02 r//rl 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 39 Z86C21 plcc 6543214443424140 18 19 20 21 22 23 24 25 26 27 28 table 2. 44-pin plcc pin identification pin # symbol function direction 14-16 p00-p02 port 0, pins 0,1,2 in/output 17 r//rl rom/romless control input 18-22 p03-p07 port 0, pins 3,4,5,6,7 in/output 23-27 p10-p14 port 1, pins 0,1,2,3,4 in/output 28 n/c not connected input 29-31 p15-p17 port 1, pins 5,6,7 in/output 32 p34 port 3, pin 4 output 33 p33 port 3, pin 3 input 34-38 p20-p24 port 2, pins 0,1,2,3,4 in/output 39 n/c not connected input 40-42 p25-p27 port 2, pins 5,6,7 in/output 43 p31 port 3, pin 1 input 44 p36 port 3, pin 6 output pin # symbol function direction 1v cc power supply input 2 xtal2 crystal, oscillator clock output 3 xtal1 crystal, oscillator clock input 4 p37 port 3, pin 7 output 5 p30 port 3, pin 0 input 6 n/c not connected input 7 /reset reset input 8 r//w read/write output 9 /ds data strobe output 10 /as address strobe output 11 p35 port 3, pin 5 output 12 gnd ground input 13 p32 port 3, pin 2 input figure 3. 44-pin plcc pin assignments
5 Z86C21 mcu with 8k rom 34 35 36 37 38 39 40 41 42 43 44 21 20 19 18 17 16 15 14 13 12 22 33 32 31 30 29 28 27 26 25 24 23 1234567891011 gnd p30 p37 xtal1 xtal2 vcc p36 p31 p27 p26 p25 /reset r//w /ds /as p35 gnd p32 p00 p01 p02 r//rl gnd p24 p23 p22 p21 p20 p33 p34 p17 p16 p15 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 gnd Z86C21 qfp table 3. 44-pin qfp pin identification pin # symbol function direction 1-5 p03-p07 port 0, pins 3,4,5,6,7 in/output 6 gnd ground input 7-14 p10-p17 port 1, pins 0 through 7 in/output 15 p34 port 3, pin 4 output 16 p33 port 3, pin 3 input 17-21 p20-p24 port 2, pins 0,1,2,3,4 in/output 22 gnd ground input 23-25 p25-p27 port 2, pins 5,6,7 in/output 26 p31 port 3, pin 1 input 27 p36 port 3, pin 6 output 28 gnd ground input 29 v cc power supply input 30 xtal2 crystal, oscillator clock output pin # symbol function direction 31 xtal1 crystal, oscillator clock input 32 p37 port 3, pin 7 output 33 p30 port 3, pin 0 input 34 /reset reset input 35 r//w read/write output 36 /ds data strobe output 37 /as address strobe output 38 p35 port 3, pin 5 output 39 gnd ground input 40 p32 port 3, pin 2 input 41-43 p00-p02 port 0, pins 0,1,2 in/output 44 r//rl rom/romless control input figure 4. 44-pin qfp pin assignments
\6 Z86C21 mcu with 8k rom pin functions /romless (input, active low). this pin, when connected to gnd, disables the internal rom and forces the device to function as a z86c91 romless z8. for more details on the romless version, refer to the z86c91 product specifica- tion. ( note: when left unconnected or pulled high to v cc , the part functions as a normal Z86C21 rom version). this pin is only available on the 44-pin versions of the Z86C21. /ds (output, active low). data strobe is activated once for each external memory transfer. for a read operation, data must be available prior to the trailing edge of /ds. for write operations, the falling edge of /ds indicates that output data is valid. /as (output, active low). address strobe is pulsed once at the beginning of each machine cycle. address output is through port 1 for all external programs. memory address transfers are valid at the trailing edge of /as. under program control, /as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/ write. xtal1, xtal2 crystal 1, crystal 2 (time-based input and output, respectively). these pins connect a parallel-reso- nant crystal, ceramic resonator, lc, or any external single- phase clock to the on-chip oscillator and buffer. r//w (output, write low). the read/write signal is low when the mcu is writing to the external program or data memory. /reset (input, active low). to avoid asynchronous and noisy reset problems, the Z86C21 is equipped with a reset filter of four external clocks (4tpc). if the external /reset signal is less than 4tpc in duration, no reset occurs. on the fifth clock after the /reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external /reset, whichever is longer. during the reset cycle, /ds is held active low while /as cycles at a rate of tpc2. when /reset is deactivated, program execution begins at loca- tion 000c (hex). power-up reset time must be held low for 50 ms, or until v cc is stable, whichever is longer. port 0 (p07-p00). port 0 is an 8-bit, nibble programmable, bidirectional, ttl compatible port. these eight i/o lines can be configured under software control as a nibble i/o port, or as an address port for interfacing external memory. when used as an i/o port, port 0 may be placed under handshake control. in this configuration, port 3, lines p32 and p35 are used as the handshake control /dav0 and rdy0 (data available and ready). handshake signal assignment is dictated by the i/o direction of the upper nibble p07-p04. the lower nibble must have the same direction as the upper nibble to be under handshake control. for external memory references, port 0 can provide ad- dress bits a11-a8 (lower nibble) or a15-a8 (lower and upper nibble) depending on the required address space. if the address range requires 12 bits or less, the upper nibble of port 0 is programmed independently as i/o while the lower nibble is used for addressing. if one or both nibbles are needed for i/o operation, they must be config- ured by writing to the port 0 mode register. in romless mode, after a hardware reset, port 0 lines are defined as address lines a15-a8, and extended timing is set to accommodate slow memory access. the initializa- tion routine includes reconfiguration to eliminate this ex- tended timing mode (figure 5).
7 Z86C21 mcu with 8k rom oen out in pa d port 0 (i/o) handshake controls /dav0 and rdy0 (p32 and p35) Z86C21 mcu 4 ttl level shifter auto latch r ? 500 k w 4 figure 5. port 0 configuration
\8 Z86C21 mcu with 8k rom pin functions (continued) port 1 (p17-p10). port 1 is an 8-bit, byte programmable, bidirectional, ttl compatible port. it has multiplexed ad- dress (a7-a0) and data (d7-d0) ports. for Z86C21, these eight i/o lines can be programmed as input or output lines or can be configured under software control as an ad- dress/data port for interfacing external memory. when used as an i/o port, port 1 can be placed under handshake control. in this configuration, port 3 line p33 and p34 are used as the handshake controls rdy1 and /dav1. memory locations greater than 8192 are referenced through port 1. to interface external memory, port 1 is programmed for the multiplexed address/data mode. if more than 256 external locations are required, port 0 must output the additional lines. port 1 can be placed in a high-impedance state along with port 0, /as, /ds and r//w, allowing the mcu to share common resource in multiprocessor and dma applica- tions. data transfers are controlled by assigning p33 as a bus acknowledge input, and p34 as a bus request output (figure 6). oen out in pa d port 1 (ad7-ad0) Z86C21 mcu ttl level shifter auto latch r ? 500 k w 8 handshake controls /dav1 and rdy1 (p33 and p34) figure 6. port 1 configuration
9 Z86C21 mcu with 8k rom port 2 (p27-p20). port 2 is an 8-bit, bit programmable, bidirectional, cmos compatible port. each of these eight i/o lines can be independently programmed as an input or output or globally as an open-drain output. port 2 is always available for i/o operation. when used as an i/o port, port 2 may be placed under handshake control. in this configuration, port 3 lines p31 and p36 are used as the handshake control lines /dav2 and rdy2. the handshake signal assignment for port 3 lines p31 and p36 is dictated by the direction (input or output) assigned to p27 (figure 7). oen out in pa d port 2 (i/o) handshake controls /dav2 and rdy2 (p31 and p36) Z86C21 mcu ttl level shifter auto latch r ? 500 k w open-drain figure 7. port 2 configuration
\10 Z86C21 mcu with 8k rom pin functions (continued) port 3 (p37-p30). port 3 is an 8-bit, cmos compatible four- fixed-input and four-fixed-output port. these eight i/o lines have four-fixed input (p33-p30) and four fixed output (p37-p34) ports. port 3, when used as serial i/o, is pro- grammed as serial in and serial out, respectively (figure 8 and table 4) port 3 pins have auto latches only. port 3 is configured under software control to provide the following control functions: handshake for ports 0 and 2 (/dav and rdy); four external interrupt request signals (irq3-irq0); timer input and output signals (t in and t out ), and data memory select (/dm). uart operation. port 3 lines p30 and p37, are be pro- grammed as serial i/o lines for full-duplex serial asynchro- out in pad Z86C21 mcu port 3 (i/o or control) auto latch r ? 500 k w pad port 3 output configuration port 3 input configuration figure 8. port 3 configuration nous receiver/transmitter operation. the bit rate is con- trolled by the counter/timer0. the Z86C21 automatically adds a start bit and two stop bits to transmitted data (figure 9). odd parity is also available as an option. eight data bits are always transmitted, regardless of parity selection. if parity is enabled, the eighth bit is the odd parity bit. an interrupt request (irq4) is generated on all transmitted characters. received data must have a start bit, eight data bits and at least one stop bit. if parity is on, bit 7 of the received data is replaced by a parity error flag. received characters generate the irq3 interrupt request.
11 Z86C21 mcu with 8k rom table 4. port 3 pin assignments pin i/o ctc1 int. p0 hs p1 hs p2 hs uart ext p30 in irq3 serial in p31 in t in irq2 d/r p32 in irq0 d/r p33 in irq1 d/r p34 out r/d dm p35 out r/d p36 out t out r/d p37 out serial out t0 irq4 t1 irq5 notes: hs = handshake signals; d = data available; r = ready auto latch. the auto latch puts valid cmos levels on all cmos inputs that are not externally driven. this reduces excessive supply current flow in the input buffer when it is not been driven by any source. low emi option. the Z86C21 is available in a low emi option. this option is mask-programmable, to be selected by the customer at the time when the rom code is submitted. use of this feature results in: n the pre-drivers slew rate reduced to 10 ns typical. n low emi output drivers have resistance of 200 ohms typical. n oscillator divide-by-two circuitry is eliminated. n internal sclk/tclk operation is limited to a maximum of 4 mhz (250 ns cycle time) p d6d5d4d3d2d1d0 start bit seven data bits received data (with parity) parity error flag one stop bit st sp p d6d5d4d3d2d1d0 start bit seven data bits transmitted data (with parity) odd parity two stop bits sp sp st d7 d6 d5 d4 d3 d2 d1 d0 start bit eight data bits transmitted data (no parity) two stop bits sp sp st d7 d6 d5 d4 d3 d2 d1 d0 start bit eight data bits received data (no parity) one stop bit sp st figure 9. serial data formats
\12 Z86C21 mcu with 8k rom functional description address space program memory. the Z86C21 can address up to 56k bytes of external program memory (figure 10). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that correspond to the six available interrupts. for rom mode, byte 13 to byte 8191 consists of on-chip rom. at ad- dresses 8192 and greater, the Z86C21 executes external program memory fetches. in the romless mode, the Z86C21 can address up to 64k bytes of external program memory. program execution begins at external location 000c (hex) after a reset. data memory (/dm). the rom version can address up to 56k bytes of external data memory space beginning at location 8192. the romless version can address up to 64k bytes of external data memory. external data memory can be included with, or separated from, the external program memory space. /dm, an optional i/o function that can be programmed to appear on p34, is used to distin- guish between data and program memory space (figure 11). the state of the /dm signal is controlled by the type instruction being executed. an ldc opcode references program (/dm inactive) memory, and an lde instruction references data (/dm active low) memory. 12 11 10 9 8 7 6 5 4 3 2 1 0 external rom and ram location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 65535 on-chip rom 8192 8191 figure 10. program memory configuration 65535 8192 8191 0 external data memory not addressable figure 11. data memory configuration
13 Z86C21 mcu with 8k rom register file. the register file consists of four i/o port registers, 236 general-purpose registers and 16 control and status registers (figure 12). the instructions can access registers directly or indirectly through an 8-bit address field. the Z86C21 also allows short 4-bit register addressing using the register pointer (figure 13). in the 4-bit mode, the register file is divided into 16 working the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register. r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4 r3 to r0 r15 to r0 ? ? ? ? ? ff f0 0f 00 1f 10 2f 20 ? ? ? ? ? ? ? ? ? stack pointer (bits 7-0) r255 stack pointer (bits 15-8) register pointer program control flags interrupt mask register interrupt request register interrupt priority register ports 0-1 mode port 3 mode port 2 mode t0 prescaler timer/counter0 t1 prescaler timer/counter1 timer mode serial i/o general-purpose registers port 3 port 2 port 1 port 0 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 r239 r3 r2 r1 r0 spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr sio p3 p2 p1 p0 r4 location identifiers register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working-register group. for the reset and power-up conditions of the register file, see figure 14. note: register bank e0-ef can only be accessed through working registers and indirect addressing modes. figure 12. register file figure 13. register pointer
\14 Z86C21 mcu with 8k rom functional description (continued) d7 d6 d5 d4 0 0 0 0 working register group pointer %ff %f0 %7f %0f %00 z8 register file register pointer % ff % fe % fd % fc % fb % fa % f9 % f8 % f7 % f6 % f5 % f4 % f3 % f2 % f1 % f0 spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr u u u 0 0 u 0 0 1 u u u u 0 u u u u 0 u 1 0 1 u u u u 0 u u u u 0 u 0 0 1 u u u u 0 u u u u 0 u 0 0 1 u u u u 0 u u u u 0 u 1 0 1 u u u u 0 u u u u 0 u 1 0 1 u u u u 0 u u u u 0 u 0 0 1 u u 0 u 0 u u u u 0 u 1 0 1 0 u 0 u 0 1111uuuu uuuuuuuu uuuuuuuu uuuuuuuu register reset condition register z8 standard control registers reset condition % (0) 03 p3 % (0) 02 p2 % (0) 01 p1 % (0) 00 p0 u = unknown d7 d6 d5 d4 d3 d2 d1 d0 s10 uuuuuu u u uuuuuu u u ? ? = for romless (z86c91) reset condition = 10110110 notes: 1. general-purpose registers are not reset after stop-mode recovery or after a reset. 2. general-purpose registers are undefined after power-up. ram protect. the upper portion of the rams address spaces 80fh to efh (excluding the control registers) can be protected from reading and writing. the ram protect bit option is mask-programmable and is selected by the customer when the rom code is submitted. after the mask option is selected, the user activates from the internal rom code to turn off/on the ram protect by loading a bit d6 in the imr register to either a 0 or a 1, respectively. a 1 in d6 indicates ram protect enabled. rom protect. the first 8 kbytes of program memory is mask programmable. a rom protect feature prevents dumping of the rom contents by inhibiting execution of ldc, ldci, lde, and ldei instructions to program memory in all modes. the rom protect option is mask-programmable, to be selected by the customer at the time when the rom code is submitted. note: with ram/rom protect on, the Z86C21 cannot access the memory space. stack. the Z86C21 has a 16-bit stack pointer (r254- r255) used for external stack that resides anywhere in the data memory for the romless mode, but only from 8192 to 65535 in the rom mode. an 8-bit stack pointer (r255) is used for the internal stack that resides within the 236 general-purpose registers (r4-r239). the high byte of the stack pointer (sph-bit 8-15) is used as a general-purpose register when using internal stack only. figure 14. ram register file reset condition
15 Z86C21 mcu with 8k rom counter/timers. there are two 8-bit programmable counter/timers (t0-t1), each driven by its own 6-bit pro- grammable prescaler. the t1 prescaler is driven by inter- nal or external clock sources; however, the t0 prescaler is driven by the internal clock only (figure 15). the 6-bit prescalers divides the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when both the counter and prescaler reach the end of the count, a timer interrupt request, irq4 (t0) or irq5 (t1), is gener- ated. the counter can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). the counter, but not the prescalers, can be read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and can be either the internal microprocessor clock divided by four, or an exter- nal signal input through port 3. the timer mode register configures the external timer input (p31) as an external clock, a trigger input that is retriggerable or non- retriggerable, or as a gate input for the internal clock. port 3, line p36, also serves as a timer output (t out ) through which t0, t1 or the internal clock is output. the counter/ timers are cascaded by connecting the t0 output to the input of t1. osc pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ? 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register ? 2 clock logic irq4 irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock ? 4 serial i/o clock tout p36 ? 2 figure 15. counter/timers block diagram
\16 Z86C21 mcu with 8k rom functional description (continued) interrupts. the Z86C21 has six different interrupts from eight different sources. the interrupts are maskable and prioritized. the eight sources are divided as follow: four sources are claimed by port 3, lines p33-p30; one in serial out, one in serial in, and two in the counter/timers (figure 16). the interrupt mask register globally or individually enables or disables the six interrupt requests. when more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the interrupt priority register. (refer to table 4.) all Z86C21 interrupts are vectored through locations in the program memory. when an interrupt machine cycle is activated, an interrupt request is granted. thus, this dis- ables all of the subsequent interrupts, save the program counter and status flags, and then branches to the program memory vector location reserved for that inter- rupt. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt in- puts are masked and the interrupt request register is polled to determine which of the interrupt requests need service. software initialed interrupts are supported by setting the appropriate bit in the interrupt request register (irq). internal interrupt requests are sampled on the falling edge of the last cycle of every instruction, and the interrupt request must be valid 5tpc before the falling edge of the last clock cycle of the currently executing instruction. for the romless mode, when the device samples a valid interrupt request, the next 48 (external) clock cycles are used to prioritize the interrupt, and push the two pc bytes and the flag register on the stack. the following nine cycles are used to fetch the interrupt vector from external memory. the first byte of the interrupt service routine is fetched beginning on the 58th tpc cycle following the internal sample point, which corresponds to the 63rd tpc cycle following the external interrupt sample point. irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 - irq5 figure 16. interrupt block diagram
17 Z86C21 mcu with 8k rom clock. the Z86C21 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 1 mhz to 16 mhz max, and series resistance (rs) is less than or equal to 100 ohms. the crystal should be connected across xtal1 and xtal2 using the recom- mended capacitors (10 pf < cl < 300 pf) from each pin 11, ground instead of just system ground. this prevents noise injection into the clock input (figure 17). note: actual capacitor value is specified by the crystal manufacturer. figure 17. oscillator configuration xtal1 xtal2 c1 c2 c1 c2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal lc clock external clock l pin 11 pin 11 pin 11 pin 11 halt. turns off the internal cpu clock but not the xtal oscillation. the counter/timers and the external interrupts irq0, irq1, irq2, and irq3 remain active. the device is recovered by interrupts, either externally or internally generated. an interrupt request must be executed (en- abled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. stop. this instruction turns off the internal clock and external crystal oscillation and reduces the standby cur- rent to 5 m a (typical) or less. the stop mode is terminated by a reset which causes the processor to restart the application program at address 000c (hex). in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user must execute a nop (opcode=0ffh) immediately before the appropriate sleep instruction. i.e., ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
\18 Z86C21 mcu with 8k rom absolute maximum ratings symbol description min max units v cc supply voltage* C0.3 +7.0 v t stg storage temp C65 +150 c t a oper ambient temp ? c stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended pe- riod may affect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 18). +5v from output under test 9.1 k w 2.1 k w 150 pf notes: * voltages on all pins with respect to gnd. ? see ordering information figure 18. test load diagram
19 Z86C21 mcu with 8k rom dc characteristics t a = 0 c t a = C40 c to +70 c to +105 c typical sym parameter min max min max @ 25 c units conditions max input voltage 7 7 v i in < 250 m a v ch clock input high voltage 3.8 v cc +0.3 3.8 v cc +0.3 v driven by external clock generator v cl clock input low voltage C0.3 0.8 C0.3 0.8 v driven by external clock generator v ih input high voltage 2 v cc +0.3 2.0 v cc +0.3 v v il input low voltage C0.3 0.8 C0.3 0.8 v v oh output high voltage 2.4 2.4 v i oh = C2.0 ma v oh output high voltage v cc C100 mv v cc C100 mv v i oh = C100 m a v ol output low voltage 0.4 0.4 v i ol = +5.0 ma v rh reset input high voltage 3.8 v cc +0.3 3.8 v cc +0.3 v v rl reset input low voltage C0.3 0.8 C0.3 0.8 v i il input leakage C2 2 C2 2 m av in = 0v, v cc i ol output leakage C2 2 C2 2 m av in = 0v, v cc i ir reset input current C80 C80 m av rl = 0v i cc supply current 30 30 20 ma [1] @ 12 mhz 35 35 24 ma [1] @ 16 mhz i cc1 standby current 6.5 6.5 4 ma [1] halt mode v in = ov, v cc @ 12 mhz 7 7 4.5 ma [1] halt mode v in = ov, v cc @ 16 mhz i cc2 standby current 10 20 1 m a [1] stop mode v in = ov, v cc i all auto latch low current C10 10 C14 14 5 m a note: [1] all inputs driven to either 0v or v cc , outputs floating.
\20 Z86C21 mcu with 8k rom ac characteristics external i/o or memory read or write timing diagram r//w 9 12 18 3 16 13 4 5 8 11 6 17 10 15 7 14 port 0, /dm port 1 /as /ds (read) port 1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 17 1 2 figure 19. external i/o or memory read/write timing
21 Z86C21 mcu with 8k rom ac characteristics external i/o or memory read or write timing table t a = 0 c to +70 ct a = C40 c to +105 c 12 mhz 16 mhz 12 mhz 16 mhz no symbol parameter min max min max min max min max units notes 1 tda(as) address valid to /as rise delay 35 25 35 25 ns [2,3] 2 tdas(a) /as rise to address float delay 45 35 45 35 ns [2,3] 3 tdas(dr) /as rise to read data reqd valid 250 180 250 180 ns [1,2,3] 4 twas /as low width 55 40 55 40 ns [2,3] 5 tdaz(ds) address float to /ds fall 0000 ns 6 twdsr /ds (read) low width 185 135 185 135 ns [1,2,3] 7 twdsw /ds (write) low width 110 80 110 80 ns [1,2,3] 8 tddsr(dr) /ds fall to read data reqd valid 130 75 130 75 ns [1,2,3] 9 thdr(ds) read data to /ds rise hold time 0000 ns [2,3] 10 tdds(a) /ds rise to address active delay 65 50 65 50 ns [2,3] 11 tdds(as) /ds rise to /as fall delay 45 35 45 35 ns [2,3] 12 tdr/w(as) r//w valid to /as rise delay 30 20 33 25 ns [2,3] 13 tdds(r/w) /ds rise to r//w not valid 50 35 50 35 ns [2,3] 14 tddw(dsw) write data valid to /ds fall (write) delay 35 25 35 25 ns [2,3] 15 tdds(dw) /ds rise to write data not valid delay 55 35 55 35 ns [2,3] 16 tda(dr) address valid to read data reqd valid 310 230 310 230 ns [1,2,3] 17 tdas(ds) /as rise to /ds fall delay 65 45 65 45 ns [2,3] 18 tddm(as) /dm valid to /as rise delay 50 30 50 30 ns [2,3] clock dependent formulas number symbol equation 1 tda(as) 0.40tpc + 0.32 2 tdas(a) 0.59tpc C 3.25 3 tdas(dr) 2.83tpc + 6.14 4 twas 0.66tpc C 1.65 6 twdsr 2.33tpc C 10.56 7 twdsw 1.27tpc + 1.67 8 tddsr(dr) 1.97tpc C 42.5 10 tdds(a) 0.8tpc 11 tdds(as) 0.59tpc C 3.14 12 tdr/w(as) 0.4tpc 13 tdds(r/w) 0.8tpc C 15 14 tddw(dsw) 0.4tpc 15 tdds(dw) 0.88tpc C 19 16 tda(dr) 4tpc C20 17 tdas(ds) 0.91tpc C10.7 18 tddm(as) 0.9tpc C 26.3 notes: [1] when using extended memory timing add 2 tpc. [2] timing numbers given are for minimum tpc. [3] see clock cycle dependent characteristics table. standard test load all timing references use 2.0v for a logic 1 and 0.8v for a logic 0.
\22 Z86C21 mcu with 8k rom ac characteristics additional timing diagram clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 9 ac characteristics additional timing table t a = 0 c to +70 c t a = C40 c to +105 c 12 mhz 16 mhz 12 mhz 16 mhz no sym parameter min max min max min max min max units notes 1 tpc input clock period 83 1000 62.5 1000 83 1000 62.5 1000 ns [1] 2 trc,tfc clock input rise & fall times 15 10 15 10 ns [1] 3 twc input clock width 35 25 35 25 ns [1] 4 twtinl timer input low width 75 75 75 75 ns [2] 5 twtinh timer input high width 3tpc 3tpc 3tpc 3tpc [2] 6 tptin timer input period 8tpc 8tpc 8tpc 8tpc [2] 7 trtin,tftin timer input rise & fall times 100 100 100 100 ns [2] 8a twil interrupt request input low times 70 70 70 50 ns [2,4] 8b twil interrupt request input low times 3tpc 3tpc 3tpc 3tpc [2,5] 9 twih interrupt request input high times 3tpc 3tpc 3tpc 3tpc [2,3] figure 20. additional timing notes: [1] clock timing references use 3.8v for a logic 1 and 0.8v for a logic 0. [2] timing references use 2.0v for a logic 1 and 0.8v for a logic 0. [3] interrupt references request through port 3. [4] interrupt request through port 3 (p33-p31). [5] interrupt request through port 30.
23 Z86C21 mcu with 8k rom ac characteristics handshake timing diagrams ac characteristics handshake timing table t a = 0 c to +70 ct a = C40 c to +105 c 12 mhz 16 mhz 12 mhz 16 mhz data no sym parameter min max min max min max min max direction 1 tsdi(dav) data in setup time 0000 in 2 thdi(dav) data in hold time 145 145 145 145 in 3 twdav data available width 110 110 110 110 in 4 tddavi(rdy) dav fall to rdy fall delay 115 115 115 115 in 5 tddavid(rdy) dav rise to rdy rise delay 115 115 115 115 in 6 tdrdyo(dav) rdy rise to dav fall delay 0000 in 7 tdd0(dav) data out to dav fall delay tpc tpc tpc tpc out 8 tddav0(rdy) dav fall to rdy fall delay 0000 out 9 tdrdy0(dav) rdy fall to dav rise delay 115 115 115 115 out 10 twrdy rdy width 110 110 110 110 out 11 tdrdy0d(dav) rdy rise to dav fall delay 115 115 115 115 out data out /dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11 data in 1 2 3 4 5 6 /dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid figure 21. input handshake timing figure 22. output handshake timing
\24 Z86C21 mcu with 8k rom d7 d6 d5 d4 d3 d2 d1 d0 serial data (d0 = lsb) r240 sio d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1 internal 0 t1 external timing input (t in ) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 z8 control register diagrams d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count t in modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) t out modes 00 not used 01 t0 out 10 t1 out 11 internal clock out r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 t1 initial value (when written) (range: 1-256 decimal 01-00 hex) t1 current value (when read) r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when written) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r244 t0 0 t0 single pass 1 t0 modulo n d7 d6 d5 d4 d3 d2 d1 d0 count mode reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0 figure 23. serial i/o register (f0 h : read/write) figure 26. prescaler 1 register (f3 h : write only) figure 28. prescaler 0 register (f5 h : write only) figure 24. timer mode register (f1 h : read/write) figure 25. counter/timer 1 register (f2 h : read/write) figure 27. counter/timer 0 register (f4 h : read/write)
25 Z86C21 mcu with 8k rom d7 d6 d5 d4 d3 d2 d1 d0 p2 0 - p2 7 i/o definition 0 defines bit as output 1 defines bit as input r246 p2m d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p0 0 - p0 0 mode 00 output 01 input 1x a 11 - a 8 stack selection 0 external 1 internal p1 7 - p1 0 mode 00 byte output 01 byte input 10 ad 7 - ad 0 11 high-impedance ad 7 - da 0 , /as, /ds, /r//w, a 11 - a 8 , a 15 - a 12 , if selected p0 7 - p0 4 mode 00 output 01 input 1x a 15 - a 12 external memory timing 0 normal 1 extended 00 p33 = input p34 = output 01 p33 = input 10 p34 = /dm 11 p33 = /dav1/rdy1 p34 = rdy1//dav1 d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 open drain 1 port 2 push-pull 0 parity off 1 parity on 0 p32 = input p35 = output 1 p32 = /dav0/rdy0 p35 = rdy0//dav0 0 p31 = input (tin) p36 = output (tout) 1 p31 = /dav2/rdy2 p36 = rdy2//dav2 0 p30 = input p37 = output 1 p30 = serial in p37 = serial out reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority reserved = 000 c > a > b = 001 a > b > c = 010 a > c > b = 011 b > c > a = 100 c > b > a = 101 b > a > c = 110 reserved = 111 irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved (must be 0) r249 ipr figure 29. port 2 mode register (f6 h : write only) figure 30. port 3 mode register (f7 h : write only) figure 31. port 0 and 1 mode register (f8 h : write only) figure 32. interrupt priority register (f9 h : write only)
\26 Z86C21 mcu with 8k rom z8 control register diagrams (continued) d7 d6 d5 d4 d3 d2 d1 d0 1 enables ram protect 1 enables irq5-irq0 (d 0 = irq0) 1 enables interrupts r251 imr d7 d6 d5 d4 d3 d2 d1 d0 r252 flags user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp 15 - sp 8 ) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp 7 - sp 0 ) r255 spl d7 d6 d5 d4 d3 d2 d1 d0 r253 rp 0 reserved (must be 0) register pointer r4 r5 r6 r7 figure 33. interrupt request register (fa h : read/write) figure 36. register pointer register (fd h : read/write) figure 35. flag register (fc h : read/write) figure 38. stack pointer register (ff h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq reserved (must be 0) irq0 = p32 input (d0 = irq0) irq1 = p33 input irq2 = p31 input irq3 = p30 input, serial input irq4 = t0 serial output irq5 = t1 figure 37. stack pointer register (fe h : read/write) figure 34. interrupt mask register (fb h : read/write)
27 Z86C21 mcu with 8k rom instruction set notation addressing modes. the following notation is used to describe the addressing modes and instruction opera- tions as shown in the instruction summary. symbol meaning irr indirect register pair or indirect working- register pair address irr indirect working-register pair only x indexed address da direct address ra relative address im immediate r register or working-register address r working-register address only ir indirect-register or indirect working-register address ir indirect working-register address only rr register pair or working register pair address symbols. the following symbols are used in describing the instruction set. symbol meaning dst destination location or contents src source location or contents cc condition code @ indirect address prefix sp stack pointer pc program counter flags flag register (control register 252) rp register pointer (r253) imr interrupt mask register (r251) flags. control register (r252) contains the following six flags: symbol meaning c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag affected flags are indicated by: 0 clear to zero 1 set to one * set to clear according to operation - unaffected x undefined
\28 Z86C21 mcu with 8k rom condition codes value mnemonic meaning flags set 1000 always true 0111 c carry c = 1 1111 nc no carry c = 0 0110 z zero z = 1 1110 nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 eq equal z = 1 1110 ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than [z or (s xor v)] = 0 0010 le less than or equal [z or (s xor v)] = 1 1111 uge unsigned greater than or equal c = 0 0111 ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 0000 f never true (always false)
29 Z86C21 mcu with 8k rom mode dst/src opc dst opc mode opc src dst opc value opc opc mode src/dst dst/src opc src/dst dst/src opc value dst opc ra dst/cc 7fh ffh 6fh opc dst dst/src 1 1 1 0 dst 1 1 1 0 src 1 1 1 0 mode src opc dst mode dst opc value opc src mode dst opc mode address x dst/src opc dau cc dal dau dal opc src 1 1 1 0 dst 1 1 1 0 dst 1 1 1 0 src 1 1 1 0 dst 1 1 1 0 clr, cpl, da, dec, decw, inc, incw, pop, push, rl, rlc, rr, rrc, sra, swap jp, call (indirect) or or or or or or or srp adc, add, and, cp, or, sbc, sub, tcm, tm, xor ld, lde, ldei, ldc, ldci ld ld djnz, jr stop/halt ld ld jp call adc, add, and, cp, ld, or, sbc, sub, tcm, tm, xor adc, add, and, cp, ld, or, sbc, sub, tcm, tm, xor one-byte instructions two-byte instructions three-byte instructions ccf, di, ei, iret, nop, rcf, ret, scf or instruction formats instruction summary note: assignment of a value is indicated by the symbol ? . for example: dst ? dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. the notation addr (n) is used to refer to bit (n) of a given operand location. for example: dst (7) refers to bit 7 of the destination operand.
\30 Z86C21 mcu with 8k rom instruction summary (continued) address instruction mode opcode flags affected and operation dst src byte (hex) c z s v d h adc dst, src ? 1[ ] [[[[ 0 [ dst ? dst + src + c add dst, src ? 0[ ] [[[[ 0 [ dst ? dst + src and dst, src ? 5[ ] - [[ 0- - dst ? dst and src call dst da d6 ------ sp ? sp C 2 irr d4 @sp ? pc, pc ? dst ccf ef [ ----- c ? not c clr dst r b0 ------ dst ? 0irb1 com dst r 60 - [[ 0- - dst ? not dst ir 61 cp dst, src ? a[ ] [[[[ -- dst C src da dst r 40 [[[ x- - dst ? da dst ir 41 dec dst r 00 - [[[ -- dst ? dst C 1 ir 01 decw dst rr 80 - [[[ -- dst ? dst C 1 ir 81 di 8f ------ imr(7) ? 0 djnz r, dst ra ra ------ r ? r C 1 r = 0 C f if r 1 0 pc ? pc + dst range: +127, C128 ei 9f ------ imr(7) ? 1 halt 7f ------ address instruction mode opcode flags affected and operation dst src byte (hex) c z s v d h inc dst r re - [[[ -- dst ? dst + 1 r = 0 C f r20 ir 21 incw dst rr a0 - [[[ -- dst ? dst + 1 ir a1 iret bf [[[[[[ flags ? @sp; sp ? sp + 1 pc ? @sp; sp ? sp + 2; imr(7) ? 1 jp cc, dst da cd ------ if cc is true c = 0 C f pc ? dst irr 30 jr cc, dst ra cb ------ if cc is true, c = 0 C f pc ? pc + dst range: +127, C128 ld dst, src r im rc ------ dst ? src r r r8 rr r9 r = 0 C f rx c7 xr d7 rir e3 ir r f3 rr e4 rir e5 rim e6 ir im e7 ir r f5 ldc dst, src r irr c2 ------ ldci dst, src ir irr c3 ------ dst ? src r ? r +1; rr ? rr + 1
31 Z86C21 mcu with 8k rom address instruction mode opcode flags affected and operation dst src byte (hex) c z s v d h stop 6f ------ sub dst, src ? 2[ ] [[[[ 1 [ dst ? dst ? src swap dstrf0x [[ x- - ir f1 tcm dst, src ? 6[ ] - [[ 0- - (not dst) and src tm dst, src ? 7[ ] - [[ 0- - dst and src xor dst, src ? b[ ] - [[ 0- - dst ? dst xor src ? these instructions have an identical set of addressing modes, which are encoded for brevity. the first opcode nibble is found in the instruction set table above. the second nibble is expressed symbolically by a [ ] in this table, and its value is found in the following table to the left of the applicable addressing mode pair. for example, the opcode of an adc instruction using the addressing modes r (destination) and ir (source) is 13. address mode lower dst src opcode nibble r r [2] r ir [3] r r [4] r ir [5] r im [6] ir im [7] instruction summary (continued) address instruction mode opcode flags affected and operation dst src byte (hex) c z s v d h nop ff ------ or dst, src ? 4[ ] - [[ 0- - dst ? dst or src pop dst r 50 ------ dst ? @sp; ir 51 sp ? sp + 1 push src r 70 ------ sp ? sp C 1; ir 71 @sp ? src rcf cf 0----- c ? 0 ret af ------ pc ? @sp; sp ? sp + 2 rl dst r 90 [[[[ -- ir 91 rlc dst r 10 [[[[ -- ir 11 rr dst r e0 [[[[ -- ir e1 rrc dst r c0 [[[[ -- ir c1 sbc dst, src ? 3[ ] [[[[ 1 [ dst ? dst ? src ? c scf df 1----- c ? 1 sra dst r d0 [[[ 0- - ir d1 srp src im 31 ------ rp ? src c 70 c 70 c 70 c 70 c 70 7430
\32 Z86C21 mcu with 8k rom 6.5 dec r1 6.5 dec ir1 6.5 add r1, r2 6.5 add r1, ir2 10.5 add r2, r1 10.5 add ir2, r1 10.5 add r1, im 10.5 add ir1, im 0123456789 abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) bytes per instruction 23 231 6.5 rlc r1 6.5 rlc ir1 6.5 adc r1, r2 6.5 adc r1, ir2 10.5 adc r2, r1 10.5 adc ir2, r1 10.5 adc r1, im 10.5 adc ir1, im 6.5 inc r1 6.5 inc ir1 6.5 sub r1, r2 6.5 sub r1, ir2 10.5 sub r2, r1 10.5 sub ir2, r1 10.5 sub r1, im 10.5 sub ir1, im 10.5 decw rr1 10.5 decw ir1 6.5 rl r1 6.5 rl ir1 10.5 incw rr1 10.5 incw ir1 6.5 cp r1, r2 6.5 cp r1, ir2 10.5 cp r2, r1 10.5 cp ir2, r1 10.5 cp r1, im 10.5 cp ir1, im 6.5 clr r1 6.5 clr ir1 6.5 xor r1, r2 6.5 xor r1, ir2 10.5 xor r2, r1 10.5 xor ir2, r1 10.5 xor r1, im 10.5 xor ir1, im 6.5 rrc r1 6.5 rrc ir1 12.0 ldc r1, irr2 18.0 ldci ir1, irr2 10.5 ld r1,x,r2 6.5 sra r1 6.5 sra ir1 20.0 call* irr1 20.0 call da 10.5 ld r2,x,r1 6.5 rr r1 6.5 rr ir1 6.5 ld r1, ir2 10.5 ld r2, r1 10.5 ld ir2, r1 10.5 ld r1, im 10.5 ld ir1, im 8.5 swap r1 8.5 swap ir1 6.5 ld ir1, r2 10.5 ld r2, ir1 6.5 ld r1, r2 6.5 ld r2, r1 12/10.5 djnz r1, ra 12/10.0 jr cc, ra 6.5 ld r1, im 12.10.0 jp cc, da 6.5 inc r1 6.0 stop 7.0 halt 6.1 di 6.1 ei 14.0 ret 16.0 iret 6.5 rcf 6.5 scf 6.5 ccf 6.0 nop 10.5 cp r1, r2 4 a lower opcode nibble pipeline cycles mnemonic second operand execution cycles upper opcode nibble first operand legend: r = 8-bit address r = 4-bit address r1 or r1 = dst address r2 or r2 = src address sequence: opcode, first operand, second operand note: blank areas not defined. * 2-byte instruction appears as a 3-byte instruction 8.0 jp irr1 6.1 srp im 6.5 sbc r1, r2 6.5 sbc r1, ir2 10.5 sbc r2, r1 10.5 sbc ir2, r1 10.5 sbc r1, im 10.5 sbc ir1, im 8.5 da r1 8.5 da ir1 6.5 or r1, r2 6.5 or r1, ir2 10.5 or r2, r1 10.5 or ir2, r1 10.5 or r1, im 10.5 or ir1, im 10.5 pop r1 10.5 pop ir1 6.5 and r1, r2 6.5 and r1, ir2 10.5 and r2, r1 10.5 and ir2, r1 10.5 and r1, im 10.5 and ir1, im 6.5 com r1 6.5 com ir1 6.5 tcm r1, r2 6.5 tcm r1, ir2 10.5 tcm r2, r1 10.5 tcm ir2, r1 10.5 tcm r1, im 10.5 tcm ir1, im 10/12.1 push r2 12/14.1 push ir2 6.5 tm r1, r2 6.5 tm r1, ir2 10.5 tm r2, r1 10.5 tm ir2, r1 10.5 tm r1, im 10.5 tm ir1, im 12.0 ldc r1, irr2 18.0 ldci ir1, irr2 12.0 lde r1, irr2 18.0 ldei ir1, irr2 12.0 lde r2, irr1 18.0 ldei ir2, irr1 opcode map
33 Z86C21 mcu with 8k rom package information 40-pin pdip package diagram 44-pin plcc package diagram
\34 Z86C21 mcu with 8k rom package information (continued) 44-pin qfp package diagram
35 Z86C21 mcu with 8k rom ordering information Z86C21 12 mhz 40-pin dip 44-pin plcc 44-pin qfp Z86C2112psc Z86C2112vsc Z86C2112fsc Z86C2112pec Z86C2112vec Z86C2112fec example: z 89c21 12 p s c environmental flow temperature package speed product number zilog prefix is a z89c21, 12 mhz, dip, 0 c to +70 c, plastic standard flow 16 mhz 40-pin dip 44-pin plcc 44-pin qfp Z86C2116psc Z86C2116vsc Z86C2116fsc zilogs products are not authorized for use as critical compo- nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 telex 910-338-7621 fax 408 370-8056 internet: http://www.zilog.com ? 1995 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of mer- chantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. for fast results, contact your local zilog sales office for assistance in ordering the part desired. codes preferred package p = plastic dip v = plastic chip carrier longer lead time f = plastic quad flat pack preferred temperature s = 0 c to +70 c longer lead time e = -40 c to +105 c speeds 12 = 12 mhz 16 = 16 mhz environmental c = plastic standard

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